SRAM memories in advanced technology nodes consume significant amount of leakage power. Powering down memories when not in use for long periods is one of the methods used to reduce overall power consumption in a system on a chip (SOC). Memories that are shared by multiple masters need special handling for power down and wakeup.
Conventionally, power-down and wake-up is software controlled by a selected one of the masters. In symmetric systems where multiple masters run code independent of each other, this requires software overhead for inter-processor communication to identify when memories can be powered down or woken up